Design of Mod 5 Synchronous Counter Using Jk Flip Flop

Complementary metal oxide semiconductor is an innovation that has changed the domain of hardware. CMOS scaling has achieved maximum limit, indicating adverse impacts not just from physical and mechanical perspective yet additionally from material and practical point of view. This drift move the analysts to search for new encouraging options in contrast to CMOS technology which indicates better execution, thickness and power utilization. To replace the CMOS technology different new technologies are developed in order to solve the different problems faced by CMOS. In this paper, new rising nanotechnology, quantum dot cellular automata is considered. Quantum dot cellular automata contributes in overcoming the difficulties faced by the CMOS technology now a days such as heat dissipation and scaling problems and hence improves the computation in different applications. For that reason, this paper propose the compatible architecture based on majority gate structures. This paper aims to present 2-bit and 3-bit synchronous counter as an application of a well-optimized JK flip-flop which is optimized on account of QCA. The proposed synchronous counter structure can be further extended to 4-bit and more. The advantage of the propound structure in comparison to previous circuits in terms of energy dissipation have been shown derived. QCADesigner E tool is used for the evaluation of the operational exactness of the designed structure.

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Design and Optimization of Synchronous

Counter Using Majority Gate-Based

JK Flip-Flop

Mehak Ishrat

1(&)

, Birinderjit Singh Kalyan

2(&)

,

Amandeep Sharma

1(&)

, and Balwinder Singh

3(&)

1

Electronics and Communication Engineering, Chandigarh University,

Punjab 140413, India

mehak.ishrat37@gmail.com, amandeep.sharma@thapar.edu

2

Electronics and Electrical Engineering, Chandigarh University,

Punjab 140413, India

birinderjit@msn.com

3

Centre for Development of Advanced Computing, Mohali, India

balwinder@cdac.in

Abstract. Complementary metal oxide semiconductor is an innovation that has

changed the domain of hardware. CMOS scaling has achieved maximum limit,

indicating adverse impacts not just from physical and mechanical perspective

yet additionally from material and practical point of view. This drift move the

analysts to search for new encouraging options in contrast to CMOS technology

which indicates better execution, thickness and power utilization. To replace the

CMOS technology different new technologies are developed in order to solve

the different problems faced by CMOS. In this paper, new rising nanotechnol-

ogy, quantum dot cellular automata is considered. Quantum dot cellular auto-

mata contributes in overcoming the diffi culties faced by the CMOS technology

now a days such as heat dissipation and scaling problems and hence improves

the computation in different applications. For that reason, this paper propose the

compatible architecture based on majority gate structures. This paper aims to

present 2-bit and 3-bit synchronous counter as an application of a well-

optimized JK fl ip-fl op which is optimized on account of QCA. The proposed

synchronous counter structure can be further extended to 4-bit and more. The

advantage of the propound structure in comparison to previous circuits in terms

of energy dissipation have been shown derived. QCADesigner E tool is used for

the evaluation of the operational exactness of the designed structure.

Keywords: QCA  Quantum dots  Quantum cells  QCA clocking 

JK fl ip fl op  Synchronous counter

1 Introduction

Moore' s law has been followed by the microelectronics industry from almost last 5

decades because of which the size and speed of electronic devices has shown the

remarkable enhancement [1 ]. According to the Moore' s law after every 18 months, on

©Springer Nature Singapore Pte Ltd. 2019

A. K. Luhach et al. (Eds.): ICAICR 2019, CCIS 1076, pp. 84– 95, 2019.

https://doi.org/10.1007/978-981-15-0111-1_9

every square inch of an integrated circuit the total number of transistors will double and

it also allows increasing the chip size as well as shrinking the size of the electronic

devices while retaining the satisfactory outcomes, hence the overall speed and the

power will also double [1 ]. Current CMOS is scaled very rapidly and continuously and

hence is ultimately reaching the fundamental deadline. Further scaling of CMOS

technology based devices is also limited by the factors such as high leakage current,

high lithography cost, quantum effects, high power dissipation and short channel effects

[2 ]. The shortcomings of the CMOS can be suppress by various emerging technologies

[3 ]. Out of the various nascent technologies, Quantum dot Cellular Automata, Single

Electron Transistor and Resonant Tunneling Diodes are few of the alternatives.

Quantum dot Cellular Automata (QCA) is the most favourable technology to take the

place of CMOS technology [1 ]. QCA is an arithmetic prototype with no transistors, in

which quantum dots are used for the implementation of cellular computation. QCA is

based on the concept of the physics of interaction between the electrons. No current

flows through the cells of the Quantum dots and the device performance is achieved by

the coupling of the cells. The binary information in QCA is represented on cells [4].

Operating speed of tetra hertz and also the device density of 10

12

devices/cm

2

can be

achieved by QCA technology. The method of computation by QCA technology offers

impressive properties of QCA such as ultra-low power dissipation, highly low power

delay product, the non-complicated interconnects, and also as the dots of the QCA are

very small in size hence it is possible to have very high packing densities and fast

operating speed of frequency range of tetra hertz [5 ]. Hence, because of the ultra-low

size feature of QCA, it is the strongest alternative to CMOS technology among the rest

[4 ]. The main advantages of QCA over CMOS technology are lesser delay, high

density circuits and low power consumption which allows us to carry out quantum

computing is not in so distant future [6].

A brief review of QCA along with clocking scheme is stated in the Sect. 2 of this

paper. Furthermore, the paper is arranged as: In Sect. 3 some related work for the

synchronous counter in QCA is discussed. In Sect. 4 , the design and implementation of

a 2-bit and 3-bit synchronous counter using J-K flip-fl op are presented. Simulation

results and waveform are shown in Sect. 5 . And in the last section of the paper

conclusion is given.

2 QCA Review

2.1 QCA Building Blocks

The primary entity of QCA is a cell. Figure 1 (1) shows schematics of QCA cell, a

regular QCA cell have four quantum dots in a square nanostructure [7 ]. Dots are said as

the places where a charge can be settled down. Each cell is fi lled with two electrons,

and these electrons tends to penetrate in between the four quantum dots of a cell.

Tunneling process only take place inside the cell and no tunneling exists among the

two cells [8 ]. In a cell, the enumeration of the quantum dots (represented by i) is started

from the top right quantum dot and then proceeds in clockwise direction [9].

Design and Optimization of Synchronous Counter 85

In QCA, binary data is represented by the place taken by the mobile electrons in all

logic cell. The electrons under the control of the timing plan are set free whenever the

barriers between the dots are very low, due to columbic repulsion these two electrons

have tendency to hold counter sites within the cell as demonstrated in Fig. 1 (1). The two

charge presentation with a polarization of − 1 and +1 is used to indicate the logic 0 and

logic 1 respectively as represented in Fig. 1 (1) [7 , 10 ]. A cell will align its polarization

with respect to its nearby driver cell whose polarization is fi xed. It has been seen that

there is extremely non-linear cell to cell interaction, which means a cell with a weak

polarization can produces an approximately completely polarized output cell. Thus,

along a line of coupled QCA cells, the data can be exchanged by communication among

adjacent cells. In QCA a wire is an arrangement of cells placed in series as represented in

Fig. 1 (2), where the cells are besides to one another. QCA gives a procedure for

exchanging data without current flow because there is no transferring of electrons

between the cells [9 ]. The easiest way to build inverter in QCA is by keeping the QCA

cells in cater-cornered position as represented in Fig. 1 (3), usually seven cells are needed

to build the inverter as shown in Fig. 1 (4) [11 ]. The output of the QCA cell has the

opposite polarization to that of the input cell. Majority gate is one of the fundamental gate

other than the inverter that is used to implement any logical calculations in QCA tech-

nology [12 ]. The majority voter and its logical symbol is shown in Fig. 1 (5) [11 , 13].

2.2 QCA Clocking

Clock signals are given to the QCA circuits to function properly, that controls and

monitors the data transferring and moreover gives the true power gain for that circuit.

QCA devices are provided with clocking system in order to provide synchronization in

implementing pipelining. The clock is applied to all the four zones, each zone com-

prises of four phases. The four phases of each zone are the switch phase, hold phase,

release phase and relax phase [6 ]. The barrier between the quantum dots of electron

location is raised or lowered by using clock signal [14].

Fig. 1. Representation of a QCA device, (1) cell; (2) wire; (3) and; (4) inverter; (5) majority

gate.

86 M. Ishrat et al.

Figure 2 represents the clocking zone and its different phases. In QCA different

colours are used to represent different clock zones, for example, in QCA Designer E

simulator, green colour is used to denote zone 0, magenta denotes zone 1, blue colour

denotes zone 2 and white colour denotes zone 3 [9].

3 Previous Works

In this section of the paper, review and analysis of counter designs have been dis-

cussed. It is much in evidence that most of the earlier research is restricted to imple-

ment small logical calculations [15 – 18 ]. In QCA up to the present time configurable

memory designs are not analysed. To depict a less complex and well organized counter

design, some work have been done up till date. Different authors put forward the

different approach for designing a sequential circuit [19 – 22 ]. A. Vetteth et al. [19]

proposed the fi rst three- input majority gate based JK flip- fl op. The associated com-

parison of the reviewed conventional design of counter in QCA is encapsulated in

Table 1.

Fig. 2. Clocking phases of clocking zone in QCA.

Table 1. Comparison of previous designs of counter using QCA technology.

S. No. References Advantages Disadvantages

1. Abutaleb et al.

[20]

Low power dissipation and low

complexity

High delay and

susceptible to noise

2. Sarmadi et al.

[21]

Low circuit complexity, high noise,

remove hardware overhead

High delay, low practical

aspect

3. Angizi et al.

[22]

Low area and cell count, low leakage

energy

Susceptible to noise, high

delay

4. Askari et al.

[23]

Low area, low cell count High delay, feedback

path

5. Khan and

Chakrabarty

[30]

Less consumption of extra area, low

expenses of designing, high reliability

Size limitation, less

effi cient usage of wire

connections

Design and Optimization of Synchronous Counter 87

Keeping in view the reduction in hardware requirements, a well-organized circuit

diagram for JK flip-fl op with reduced circuit design [31 ] is extremely favourable in

designing various sequential circuits. The schematic diagram of JK flip-fl op demon-

strated in Fig. 3 , is made up of four majority gates and two inverters [31].

Q out ðÞ¼ JQ0 þK 0 Q ð1 Þ

The complement of input K is fed to one of input of the majority gate M1 and the

output Q is feedback to the circuit to another input of the majority gate M1. The output

JQ′ +KQ ′is produced from the majority gate M2 which acts as OR gate. The clock

input combined with the output of M1 and M3 are fed to the inputs of the majority gate

M2. Equation (1 ) produces the desired characteristics of JK fl ip flop.

4 Proposed Work

4.1 Implementation of JK Flip-Flop

Flip-fl ops are the basic structural constituents for designing sequential circuits. Output

of the flip-fl ops depends on both the present input and the previous output [15 ]. It is a

primary one bit element in a sequential circuit that acts as binary storage [12 ]. In order

to implement the proposed synchronous counter, the schematic of JK flip-fl op in Fig. 3

is accomplished by using the three input majority gate structure. The schematic layout

of JK fl ip-fl op in QCA is shown in Fig. 4.

Fig. 3. Majority gate based JK fl ip flop.

Fig. 4. Layout of JK fl ip fl op in QCA.

88 M. Ishrat et al.

4.2 Proposed Design of Synchronous Counter

Synchronous counters are widely employed in digital circuits using four types of flip-

flops. The application of synchronous counters are to divide frequency, count time and

pulse [11 ]. This section of the paper presents a highly optimized confi guration of a n-bit

synchronous counter. In synchronous counter each flip-fl op is triggered via a single

clock pulse. The counter output continuously changes depending on the either edge of

the clock. The proposed mod-4 (2-bit) synchronous counter can further be modifi ed to

mod-8 (3 bit), mod-16 (4-bit) and more. The purposed design is composed of JK flip-

flop and other combinational logic circuits.

As illustrated in Figs. 5 and 6 , the purposed synchronous counter is comprised of

two JK fl ip-fl ops which are connected together and edge triggering mechanism is

provided by connecting each JK flip-fl op to a single clock. This paper presents only 2-

bit and 3-bit synchronous counter. In the proposed architecture of synchronous counter,

two JK flip-fl ops are employed and are clocked by a single clock simultaneously. The

presented design of synchronous counter can be expanded in an n-bit synchronous

counter.

Fig. 5. Proposed QCA-based 2-bit synchronous counter. (1) block diagram, (2) schematic

diagram and (3) QCA layout.

Design and Optimization of Synchronous Counter 89

5 Results and Discussion

QCADesigner E bistable engine is used to validate the functionality of the purposed

designs. In this section of the paper, the proposed synchronous counter is simulated

using QCADesigner E tool. The remaining part of this section presents the simulation

process.

Fig. 6. Proposed QCA-based 3-bit synchronous counter. (1) block diagram, (2) schematic

diagram and (3) QCA layout.

Fig. 7. Simulation waveform of 2-bit synchronous counter.

90 M. Ishrat et al.

QCADesigner E tool is used for the simulation purpose of the purposed designs, it

also contributes in optimization of power consumption to the best possible extent. As

illustrated in Fig. 5 (3), the output (Q1) of the fi rst flip- fl op is linked to the inputs (J &

K) of the next flip- fl op. The working of the proposed synchronous counter can be

explained such that a 2-bit synchronous counter have two outputs and one input called

sel (select). Therefore, for a 3-bit synchronous counter, there are three outputs and one

input. For a 2-bit synchronous counter, 2

2

i.e. 4 combinations of output are formed.

A selection line which acts as the enable signal is provided to the proposed syn-

chronous model to produce output of the proposed model, which means sel (select) line

controls the on and off series of the circuit. The mentioned operation is based on the

low or high input at the sel (selection) line. The simulation waveform of the purposed

2-bit and 3-bit counter is presented in Figs. 7 and 8 respectively. To check the design

functionality of the proposed counter QCADesigner E tool has been used. The accurate

function of the purposed 2-bit synchronous counter is verifi ed by the Fig. 7 . From the

simulation results, the counting operation is correctly realized for outputs-Q0 and Q1.

5.1 Comparison

The proposed synchronous counters are compared with the previous designs of syn-

chronous counters and is summarized in Table 2 . Clearly it is noticeable that the

purposed design results in signifi cant advancement in respect of complexity, area

occupied and latency in contrast to the prior designs.

The proposed 2-bit and 3-bit synchronous counter uses 123 and 226 cells respec-

tively. The latency for the proposed counters is 1 clock cycle, which is a very low

latency. By minimizing the cells count and occupied area of the design, power dissi-

pation of the design can be reduce.

The total energy dissipation (Sum_Ebath) of 2-bit synchronous counter using the

QCADesigner E tool obtained is 3.56e-002 eV (Error: +/−− 2.88e-003 eV) and the

average energy dissipation per cycle (Avg_Ebath) of 2-bit synchronous counter

obtained is 3.23e-003 eV (Error: +/−− 2.62e-004 eV). The total energy dissipation

(Sum_Ebath) and the average energy dissipation per cycle (Avg Ebath) of 3-bit syn-

chronous counter using QCADesigner E tool obtained are 6.05e-002 eV (Error: +/−

Fig. 8. Simulation waveform of 3-bit synchronous counter.

Design and Optimization of Synchronous Counter 91

−4.71e-003 eV) and 5.50e-003 eV (Error: +/ −− 4.28e-004 eV) respectively. Keeping

in view the values of energy dissipation attained through QCADesigner E tool, Figs. 9

and 10 illustrate the noticeable optimization in power dissipation of proposed 2-bit and

3-bit synchronous counter respectively.

Table 2. Comparison of existing QCA-based synchronous counter designs.

Design Area (µm

2

) Complexity (cell counts) Latency (clock cycle)

2-bit synchronous counter

C.-B. Wu et al. [24 ] 0.74 430 4

S. Sheikhfaal et al. [25 ] 0.26 240 2

S. Angizi et al. [26 ] 0.22 141 2.25

A. M. Chabi et al. [27 ] 0.67 464 5.75

M. Goswami et al. [28 ] 0.62 328 3

Proposed 2-bit counter design 0.11 123 1

3-bit synchronous counter

C.-B. Wu et al. [24 ] 1.02 677 6

S. Sheikhfaal et al. [25 ] 0.48 428 2

S. Angizi et al. [26 ] 0.36 328 2.25

M. Abutaleb et al. [20 ] 0.22 196 5.75

M. Goswami et al. [28 ] 1.18 786 7.75

Proposed 3-bit counter design 0.24 226 1

-0.001

0

0.001

0.002

0.003

0.004

1234567891011

E_Error_total:

E_clk_total:

E_bath_total:

Fig. 9. The illustration of energy dissipation of 2-bit synchronous counter.

92 M. Ishrat et al.

6 Conclusion

With the unique specifi cations Quantum dot cellular automata decreases the physical

limit of CMOS devices realization. Hence it inspires researchers to bring into play the

QCA technology for designing various integrated circuits. This paper brings a well

effi cient realization of synchronous counter design using well-optimized JK flip-flops.

Less cell count, low area consumption and delay are considered as the advantages of

the proposed design in contrast to the available designs. QCADesigner tool is used for

the QCA layout and validation of purposed designs. A well considerable improvement

in respect of area, complexity and delay of proposed synchronous counter is visible

from the simulation results and a comprehensive contrast among the proffered and the

previous counter designs have been derived in regards of power dissipation, area and

hardware complexity. The comparisons verify that the presented design of this paper is

more advantageous in all the mentioned parameters. Moreover, effi cient 4 bit and n-bit

QCA based synchronous counters from the proposed design can be constructed. It is

feasible to employ the purposed design as a basic sequential component for a larger

QCA designs such as memory units, nano processor and ALU. It can be concluded that

the clock delay of QCA-based circuits is very low and can be even neglected.

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-0.002

-0.001

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

1234567891011

E_Error_total:

E_clk_total:

E_bath_total:

Fig. 10. The illustration of energy dissipation of 3-bit synchronous counter.

Design and Optimization of Synchronous Counter 93

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Design and Optimization of Synchronous Counter 95

ResearchGate has not been able to resolve any citations for this publication.

• Zaman Amirzadeh
• Mohammad Gholami

The quantum-dot cellular automata (QCA) were highly regarded due to its high operating frequency and significantly low power consumption. One of the most useful circuits in processors architecture is counter. This paper presents effective designs and arrangement of QCA based counter-circuits. In this study new counter circuits in QCA technology are designed and precise simulation are done using the QCADesigner. Three, four and five bits counters are proposed in this paper in QCA technology. A comparison is made between the past and recent designs to illustrate which method is better and more efficient in terms of area, complexity, number of cells, and delay. For example, the proposed three bit shift register has 174 quantum cells, 0.2μm² occupied area and three QCA clock cycles delay.

Quantum-dot cellular automata (QCA) is one of the emergent nano-technologies and a potential substitute for transistor based technologies. In this research, an efficient QCA based T, SR and JK flip-flops have been proposed. The proposed gates are implemented with multiplexer, three-input Majority gate and XOR gate. The circuit layouts are designed and verified using QCADesigner version 2.0.3. The simulation result reviles the excellence of the proposed design. The proposed T flip-flop archives 35% improvement in terms cell count. Similarly, the reported RS and JK flip-flop requires 43% and 50% less area respectively in comparison to the previous best single layer design. In addition, QCAPro tool has been used to estimate the power dissipation of all considered designs at different tunneling energy level.

• Mojtaba Gholamnia Roshan
• Mohammad Gholami

Emerging nanotechnology of Quantum-dot Cellular Automata (QCA) is one of the alternative technologies for CMOS technology. One of the essential parts of the structure of each arithmetic and logic units on the processors is the circuits that are affiliated with the Flip-Flops. Therefore, considering the importance of D Flip-Flops among different types of Flip-Flops and their more efficient performance, this paper presents new structures for D Latch and D Flip-Flops in QCA nanotechnology. First, the proposed D latch in QCA technology which has only 19 cells and a delay of 0.75 cycles is reported and will be compared with previous works. The comparison shows that the proposed D latch has the fewer number of cells, smaller area, and less delay. Then there are some methods for converting proposed latch into Flip-Flops, and with the help of these, new proposed falling edge, rising edge and dual edge triggered D Flip-Flops are suggested. The proposed structures have been designed in one layer. In terms of occupied area, delay and number of cells, the proposed D Flip-Flops are superior to previous structures. At last, set and reset pins will be added to proposed designs, and this is another advantage of proposed circuits, which is rarely seen in previous structures.

Fast pace growth in the IC industry is facing the challenges of feature size reduction which in turn demands an alternative to current CMOS VLSI. Quantum-dot cellular automata are emerging as one of the viable alternative nanotechnologies with high device density, high operating frequency and low power characteristics. Information transition and propagation in QCA take place with the underlying clocking circuitry. Thus, clocking is the main source of power of the QCA circuit as well as play the vital role of information synchronisation in QCA circuit. For efficient design and to provide routing option, a regular, scalable clocking structure becomes the utmost necessity of QCA circuit. In this context, a robust, efficient and scalable (RES) clocking scheme for QCA circuit is proposed which can facilitate three directional information flow within a single clock zone. Also, it can facilitate the feedback path without extra layer (unlike 2DDwave scheme) and overcome the complex multilayer wire crossing (unlike USE scheme) with most promising coplanar crossover. Simulation results underpin the significant improvement in terms of clocking zone, area and cells.

• Birinderjit Singh Kalyan

The Quantum-dot Cellular Automata (QCA) is a replacement of the conventional CMOS Technology for nano computing devices. This technology aids to achieve extra low power, lower complexity sequential structures with very high speed. In this paper JK flip flop is redesigned and compared with previous structures. The JK flip flop based QCA structure which has 78% lesser complexity and covered 66.6 % less area with half latency than previous designs. Further the novel 4 bit shift register was designed as well as simulated in QCA designer tool using proposed JK flip flop. The total area covered by shift register is 0.20 µm2 with single clock cycle delay. The power estimation is done in QCAPro tool.

Quantum Dot Cellular Automata (QCA) is a newly developed paradigm for digital design, which holds the potential as possible alternative to the present Complementary Metal Oxide Semi-Conductor (CMOS) technology. After surviving for nearly five decades, the scaling of CMOS is finally reaching its limits. The asperities are not only seen from the physical and technological viewpoint but also from the material and economical perspectives. With no more scaling possible, there is a need to look for promising alternatives to continue with the nano size/scale computations and to hold on to the Moore's law. QCA offers a breakthrough required for the fulfilment of certain lacking aspects of CMOS technology in the nano regime. QCA is a technology that involves no current transfer but works on electronic interaction between the cells. The QCA cell basically consists of quantum dots or metal islands separated by certain distance and the entire transmission of information occurs via the interaction between the electrons localized in the potential wells. Since the technology is new and in a premature phase, a huge scope lies ahead of the researchers to investigate and make QCA design a reality. In this paper the QCA technology is reviewed with sufficient focus on basic concepts, implementations and information flow. The various building blocks in QCA are discussed and their working on the basis of physical laws is explained. This paper forms the basis for further complex digital designing in QCA.

Quantum-dot Cellular Automata (QCA) is a very interesting nano-scale technology. Extremely small feature size and ultra-low power consumption are the most important features of QCA compared to CMOS. Counters are considered as one of the most fundamental components in sequential circuits. Previous QCA synchronous counters (QSCs) have been designed and simulated using two methods. In the first method, QSCs utilize direct mapping flip-flop designs in CMOS technology to QCA. In the second method, QSCs are designed with the inherent capability of QCA technology. Despite being attractive, mentioned approaches have constraints (i.e. long wire length and area issues). In this brief, design and simulation of a QSC are presented through combining the two approaches. Experimental results reveal that the novel combination not only overcomes limitations of the above methods, but also improves delay and cost function (at least two times lower than the best previous QSCs).

Design of Mod 5 Synchronous Counter Using Jk Flip Flop

Source: https://www.researchgate.net/publication/335852161_Design_and_Optimization_of_Synchronous_Counter_Using_Majority_Gate-Based_JK_Flip-Flop